The present invention relates to a method of manufacturing a semiconductor device functioning as a Bi-CMOS including a high frequency bipolar transistor and a MOS transistor mounted on a common substrate.
Typical examples of transistors generally used at present include a bipolar transistor comprising an emitter, a base and a collector and a MOS transistor comprising a gate electrode, a gate oxide film and source/drain regions. A bipolar transistor is characterized by being suitably used in an analog device due to its linear amplifying function, and a MOS transistor is characterized by its simple structure and being suitably used in a logic element. Recently, a bipolar transistor is more widely used as a high frequency transistor, and there is a demand for a transistor suitable to a higher frequency. On the other hand, higher integration is required of a MOS transistor.
Furthermore, a semiconductor device using a high frequency bipolar transistor and a MOS transistor is recently required to be more compact. In order to attain compactness of such a semiconductor device, it is effective to build the semiconductor device in one chip with both the transistors mounted on a common substrate. Accordingly, the so-called Bi-CMOS device including a bipolar transistor and a MOS transistor mounted on a common substrate has been proposed.
Now, a conventionally proposed method of manufacturing a Bi-CMOS device will be described with reference to accompanying drawings. FIGS. 16 through 24 are sectional views for showing conventional manufacturing procedures for the Bi-CMOS device.
First, in the procedure shown in FIG. 16, a main surface of a p-type silicon substrate 101 is oxidized, thereby forming a silicon oxide film thereon. The silicon oxide film is then etched by using a photoresist film (not shown) formed by the lithography on the silicon oxide film as a mask, so as to selectively remove the silicon oxide film. Thus, a mask oxide film 106 having an opening in a bipolar transistor forming region Rbp and an opening in a MOS transistor forming region Rmos is formed.
Next, by using the mask oxide film 106 as a mask, arsenic ions 107 are implanted into the main surface of the p-type silicon substrate 101 under conditions of, for example, at an acceleration energy of 30 keV and a dose of 1.5.times.10.sup.15 cm. Thus, deep ion implanted layers 102 and 103 are formed respectively in the bipolar transistor forming region Rbp and the MOS transistor forming region Rmos.
Then, a heating treatment is conducted so that the arsenic in the deep ion implanted layers 102 and 103 can be diffused and the deep ion implanted layers 102 and 103 can be oxidized for forming a step for patterning. The mask oxide film 106 is then entirely removed.
Next, in the procedure shown in FIG. 17, an epitaxial layer 105 is grown on the entire main surface of the p-type silicon substrate 101. At this point, the arsenic is partially diffused from the deep ion implanted layers 102 and 103 formed along the main surface of the p-type silicon substrate 101 into the epitaxial layer 105, thereby forming n-type buried layers 108 and 109.
Then, a silicon oxide film 110 and an active region forming silicon nitride film 111 are successively formed on the epitaxial layer 105. Thereafter, openings are formed in the active region forming silicon nitride film 111 correspondingly to the bipolar transistor forming region Rbp and a PMOSFET forming region Rpmos in the MOS transistor forming region Rmos. Phosphorus ions 112 are implanted through these openings, thereby forming surface diffusion layers 113 in the bipolar transistor forming region Rbp and the PMOSFET forming region Rpmos.
Next, in the procedure shown in FIG. 18, the silicon oxide film 110 is removed, and a silicon region in each opening is selectively oxidized, thereby forming a mask oxide film 115. Through the heat treatment for this oxidation, the impurity in the surface diffusion layer 113 is widely diffused, and hence, an n-type well region 114 is formed and the n-type buried layers 108 and 109 are enlarged in their depths.
Subsequently, in the procedure shown in FIG. 19, boron ions 116 are implanted into an NMOSFET forming region Rnmos in the MOS transistor forming region Rmos and the like by using the mask oxide film 115 as a mask, thereby forming a p-type implanted layer.
Then, in the procedure shown in FIG. 20, the mask oxide film 115 is removed and drive-in is conducted through a heat treatment, thereby forming a p-type well region 117. Through this heat treatment, the N-type buried layers 108 and 109 are further enlarged in their depths.
Next, in the procedure shown in FIG. 21, after forming a LOCOS forming silicon nitride film 118 on the substrate, isolation oxide films 119a through 119e are formed in predetermined isolation regions by the general LOCOS method.
Then, in the procedure shown in FIG. 22, after growing a silicon oxide film 120 on the substrate, the isolation oxide films 119a and 119c including portions directly above the edges of the n-type buried layer 109 in the bipolar transistor forming region Rbp and substantially the center portions of the silicon oxide film 120 above the isolation oxide films 119a and 119c are selectively removed. Thus, trench openings 121 are formed.
Subsequently, in the procedure shown in FIG. 23, the silicon substrate exposed within each trench opening 121 is etched by using the silicon oxide film 120 as a mask, thereby forming a trench 122 with a depth of approximately 5 through 6 .mu.m.
Furthermore, in the procedure shown in FIG. 24, after forming a channel stopper layer 123 below the bottom of each trench 122, a sidewall oxide film 124 of the trench 122 is formed. Then, the trench 122 is buried with polysilicon, thereby forming a buried polysilicon layer 125. The buried polysilicon layer 125 is formed by depositing a polysilicon layer on the substrate and etching back the polysilicon film through the dry etching.
The procedures thereafter are not described in detail, through which diffusion layers, electrodes and the like of a bipolar transistor, a PMOSFET and an NMOSFET are formed.
The Bi-CMOS device manufactured in the aforementioned manner can exhibit the following effects because it adopts a trench isolation structure instead of a LOCOS isolation structure: Due to the trench isolation structure, the junction capacitance between a collector in the bipolar transistor forming region Rbp and the substrate can be decreased, resulting in making the bipolar transistor applicable to a higher frequency. Also, since the trench isolation structure is adopted instead of the LOCOS isolation structure, the width of the isolation oxide films 119a through 119e can be decreased as compared with that of PN junction isolation. As a result, the line capacitance can be decreased and the device is applicable to a further higher frequency.
In forming the isolation, the trench is buried not with a silicon oxide film, which is used in a trench structure in a MOS transistor, but with polysilicon. This is for the following reasons: First, since it is necessary to conduct a heat treatment at a high temperature of approximately 900.degree. C. after forming the trench isolation in manufacturing a bipolar transistor, occurrence of defects in the active region derived from a difference in the coefficient of thermal expansion between the silicon substrate and the material within the trench is thus avoided. Secondly, polysilicon in a small grain size having directivity is good in a burying characteristic such as coverage in a groove much deeper than a trench isolation of a MOS transistor, and hence, occurrence of voids unavoidable in using a silicon oxide film can be thus avoided. Accordingly, the trench is buried with polysilicon, and the sidewall oxide film 124 is formed between the buried polysilicon layer 125 and the p-type silicon substrate 101.
Thereafter, although not shown in the drawings, a region directly below the exposed surface of the buried polysilicon layer 125 is oxidized, thereby forming a cap oxide film integrated with the isolation oxide films 119a and 119c. In this manner, it is possible to prevent formation of an unwanted transistor and occurrence of an unwanted capacitance otherwise caused by the buried polysilicon layer 125 activated by an introduced impurity.
However, the aforementioned conventional method of manufacturing a Bi-CMOS device has the following problems:
First, in the state shown in FIG. 23, the n-type buried layers 108 and 109 are expanded through the heat treatment for forming the n-type well region 114 and the p-type well region 117. Specifically, in forming a high frequency bipolar transistor and a highly integrated CMOS transistor on a common substrate, the heat treatment for activating p-type and n-type wells of the CMOS transistor should be conducted at a high temperature for a long period of time. Therefore, the n-type buried layers 108 and 109 in the bipolar transistor forming region are unavoidably enlarged. Accordingly, in order to guarantee the isolation function, it is necessary to deepen the trench 122 penetrating the n-type buried layer 109 in the bipolar transistor forming region Rbp to a depth of approximately 5 through 6 .mu.m. This results in disadvantageously excessively increasing the time required for forming the trench 122, and the procedure is practically difficult to conduct.
Since the conventional method of manufacturing a Bi-CMOS device has the aforementioned disadvantage, a Bi-CMOS device including a high frequency bipolar transistor and a CMOS transistor mounted on a common substrate has been difficult to realize.
Also, in removing the silicon oxide film 120 used as a mask in forming the trench in the subsequent procedure, the isolation oxide films 119b, 119d and 119e below the silicon oxide film 120 are also partially removed. This results in degrading the isolation function in the MOS transistor forming region.
Secondly, as is shown in FIG. 24, in the buried polysilicon layer 125 formed by etching back the polysilicon film, the surface can cave in at the center in a V shape as a V groove 126. After forming the buried polysilicon layer 125, an oxide film and a line are formed thereon, and a bridge can be formed and the line can be broken due to this V groove 126.
The present inventors have examined the cause of the formation of this V groove, and have found the following phenomenon as the cause:
As is shown in FIG. 14, in growing the polysilicon film in the trench, pillar-shaped crystal grains are grown in a direction perpendicular to the wall of the trench 122, that is, a direction of temperature gradient. As a result, the tips of the pillar-shaped crystal grains are gathered at the center of the trench 122. Specifically, crystal boundaries are gathered at the center of the trench 122, and a much larger number of defects are present at the center than in other areas. However, in general, the etch rate is much higher in an area including a large number of defects than in an area including a small number of defects. Accordingly, the V groove 126 is formed at the center of the resultant buried polysilicon layer 125.
Such a phenomenon occurs not only in a buried polysilicon layer of a trench in a Bi-CMOS device but also in a buried polysilicon layer in another type of semiconductor device. Also, there is possibility of the occurrence of this phenomenon in etching back another insulating material apart from polysilicon used for burying in a trench.